Field
Implementations described herein generally relate to semiconductor manufacturing, and, more specifically, to methods of selectively forming silicon oxide films.
Description of the Related Art
As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form those IC's is increased. With increased element density, the dimensions, size and spacing between the individual components or elements is reduced. Increased resolution from patterning processes is one mechanism for reduction in size and spacing of features on an IC.
Increased resolution can be achieved by altering the intrinsic resolution of the pattern. The intrinsic resolution of a pattern is the finest spatial detail that a pattern can transfer. The intrinsic resolution is a function of factors such as the wavelength of radiation used and the size of the features in a pattern. Pattern multiplication processes, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP), can be used to increase the resulting resolution of a patterning process without changing the intrinsic resolution of exposure tools. Thus, these processes can decrease the number of lithography exposures per layer, which decreases a significant cost in device fabrication.
Current pattern multiplication is usually achieved by the combination of several deposition and etch steps. Such approach is highly cost inefficient, and may create significant integration complexity. Further, as feature sizes becomes smaller
Therefore, there is a need for new methods of controlling feature size in ICs.